Digitally adjustable picosecond delay circuit
US5506534A · kind A · utility
33Cited by
15References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | May 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.