Global planarization process using patterned oxide
US5508233A · kind A · utility
18Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1994 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Oct 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing the surface of a layer in a semiconductor device includes forming conductor regions 24, 26, and 28 on a layer of the semiconductor device; forming first insulator regions 30, 32, and 34 in gaps between the conductor regions 24, 26, and 28; and forming an insulator layer 40 over the first insulator regions 30, 32, and 34, and over the conductor regions 24, 26, and 28 such that a surface of the insulator layer 40 will be substantially planar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.