Multi-path data synchronizer system and method
US5509038A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 1994 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Apr 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and retains the current state of comparison at the start of a transfer of a block or frame of data for determining along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. A phase comparator responds to the phase relationship between clocks attaining a value within one or another range of values at the start of a data frame to determine which one of the multiple data paths transfers the data frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.