Thomas M. Wicki
28Patents
15h-index
35Co-inventors
81Inventor score
Filing activity: Apr 6, 1994 → Feb 10, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5892766A | Method and apparatus for coordinating access to an output of a routing device in a packet switching network | Electricity | 126 | Expired |
| US5838684A | Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method | Electricity | 98 | Expired |
| US5959995A | Asynchronous packet switching | Electricity | 94 | Expired |
| US6119205A | Speculative cache line write backs to avoid hotspots | Physics | 84 | Expired |
| US6393023B1 | System and method for acknowledging receipt of messages within a packet based communication network | Electricity | 69 | Expired |
| US5509038A | Multi-path data synchronizer system and method | Electricity | 48 | Expired |
| US5740346A | System and method for dynamic network topology exploration | Electricity | 45 | Expired |
| US6912628B2 | N-way set-associative external cache with standard DDR memory devices | Physics | 45 | Expired |
| US6122709A | Cache with reduced tag information storage | Physics | 39 | Expired |
| US6212602A | Cache tag caching | Physics | 35 | Expired |
| US6003064A | System and method for controlling data transmission between network elements | Electricity | 28 | Expired |
| US5987629A | Interconnect fault detection and localization method and apparatus | Electricity | 25 | Expired |
| US5931967A | Method and apparatus for detection of errors in multiple-word communications | Electricity | 22 | Expired |
| US6832294B2 | Interleaved n-way set-associative external cache | Physics | 16 | Expired |
| US5768300A | Interconnect fault detection and localization method and apparatus | Electricity | 15 | Expired |
| US6269426A | Method for operating a non-blocking hierarchical cache throttle | Physics | 13 | Expired |
| US6154815A | Non-blocking hierarchical cache throttle | Physics | 11 | Expired |
| US6684299B2 | Method for operating a non-blocking hierarchical cache throttle | Physics | 7 | Expired |
| US7523342B1 | Data and control integrity for transactions in a computer system | Electricity | 7 | Active |
| US7366843B2 | Computer system implementing synchronized broadcast using timestamps | Physics | 5 | Expired |
| US7609092B2 | Automatic phase-detection circuit for clocks with known ratios | Physics | 3 | Active |
| US9921899B2 | Monitoring serial link errors | Electricity | 1 | Active |
| US9285865B2 | Dynamic link scaling based on bandwidth utilization | Emerging Cross-Sectional Technologies | 0 | Active |
| US10387314B2 | Reducing cache coherence directory bandwidth by aggregating victimization requests | Physics | 0 | Active |
| US11507414B2 | Circuit for fast interrupt handling | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.