Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths
US5511174A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Aug 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30149
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for selectively controlling the operation of a computer system so that the computer system is selectively caused to execute instructions of a first predetermined bit length or instructions of a second predetermined bit length. The method comprises the preliminary steps of storing instruction data in a set of EVEN instruction storage locations; storing instruction data in a set of ODD instruction locations; establishing an EVEN execution pointer; and establishing an ODD execution pointer. At a first given time, either the EVEN execution pointer is incremented by a predetermined COUNT or the ODD execution pointer is incremented by the predetermined COUNT; but both pointers are not simultaneously incremented by the COUNT. The method causes an instruction to be executed, which instruction was stored entirely in either an EVEN instruction location or entirely in an ODD instruction location. At a second given time, both the EVEN instruction pointer and the ODD instruction pointer are incremented by the predetermined COUNT, thereby causing an instruction to be executed, which instruction constitutes a combination of instruction data from an EVEN instruction storage location and i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.