Clock recovery phase locked loop control using clock difference detection and forced low frequency startup
US5512860A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1994 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Dec 2, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and outputting output clock pulses from the phase locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.