Method and apparatus for interconnect testing without speed degradation
US5513186A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 1993 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Dec 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The present invention provides a full boundary scan test capability with practically no degradation of speed of operation during normal operation of the integrated circuit. Within the integrated circuit under test, boundary scan registers are coupled to each input and bi-directional pin. When placed in a test mode, the corresponding output drivers are tristated for every bi-directional pin of the integrated circuit under test. Then the values of a test signal vector asserted on the pins of the integrated circuit are captured by the boundary scan registers. These captured values are retrieved and output from the integrated circuit so that they can be compared to the asserted test signal vector. Because the integrated circuit does not have any non-test specific output pins, there is no need to override values output from the integrated circuit during a full boundary scan test. Furthermore, because the boundary scan registers capture the test signal vector values but cannot override values, the prior art need to provide a multiplexer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.