Method for generating hierarchical fault-tolerant mesh architectures
US5513313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1995 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Aug 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware architecture. Typically, the hardware mesh architecture includes redundant nodes and interconnections, sot hat the target logical mesh architecture may be defined from the hardware architecture several different ways. As a consequence, the target logical mesh architecture may be defined even in the presence of faulty nodes or interconnections in the hardware architecture. Frequently, the logical mesh is defined in terms of some regular pattern of interconnections. The method of the invention facilitates the definition of the desired logical mesh architecture from the hardware architecture, given the possibility that one or more faults are present, by initially defining logical blocks of nodes from among the functional nodes of the hardware architecture. Then, functional edges between the nodes defined within the logical blocks are defined as logical interconnections between the nodes of the lo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.