Robert E. Cypher
138Patents
22h-index
45Co-inventors
90Inventor score
Filing activity: Jun 28, 1991 → Mar 28, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8856619B1 | Storing data across groups of storage nodes | Physics | 368 | Active |
| US8640000B1 | Nested coding techniques for data storage | Electricity | 166 | Active |
| US6976194B2 | Memory/Transmission medium failure handling controller and method | Physics | 121 | Expired |
| US6973613B2 | Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure | Physics | 120 | Expired |
| US6996766B2 | Error detection/correction code which detects and corrects a first failing component and optionally a second failing component | Physics | 58 | Expired |
| US5513371A | Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations | Physics | 48 | Expired |
| US5280607A | Method and apparatus for tolerating faults in mesh architectures | Physics | 43 | Expired |
| US6477682B2 | Technique for partitioning data to correct memory part failures | Physics | 41 | Expired |
| US6453440B1 | System and method for detecting double-bit errors and for correcting errors due to component failures | Physics | 40 | Expired |
| US7412642B2 | System and method for tolerating communication lane failures | Electricity | 38 | Active |
| US6473880B1 | System and method for protecting data and correcting bit errors due to component failures | Physics | 35 | Expired |
| US7188296B1 | ECC for component failures using Galois fields | Electricity | 34 | Expired |
| US5444701A | Method of packet routing in torus networks with two buffers per edge | Electricity | 34 | Expired |
| US6768640B2 | Computer system employing redundant cooling fans | Electricity | 32 | Expired |
| US7676636B2 | Method and apparatus for implementing virtual transactional memory using cache line marking | Physics | 31 | Active |
| US6304992A | Technique for correcting single-bit errors in caches with sub-block parity bits | Physics | 30 | Expired |
| US5513313A | Method for generating hierarchical fault-tolerant mesh architectures | Physics | 30 | Expired |
| US6282686A | Technique for sharing parity over multiple single-error correcting code words | Physics | 30 | Expired |
| US8484438B2 | Hierarchical bloom filters for facilitating concurrency control | Physics | 27 | Active |
| US7318114B1 | System and method for dynamic memory interleaving and de-interleaving | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7917698B2 | Method and apparatus for tracking load-marks and store-marks on cache lines | Physics | 23 | Active |
| US7050307B2 | Circuit board orientation in a computer system | Electricity | 22 | Expired |
| US6484240B1 | Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols | Physics | 21 | Expired |
| US7117312B1 | Mechanism and method employing a plurality of hash functions for cache snoop filtering | Physics | 21 | Expired |
| US6141789A | Technique for detecting memory part failures and single, double, and triple bit errors | Physics | 21 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.