Integrated circuit I/O using a high performance bus interface
US5513327A · kind A · utility
218Cited by
58References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1994 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Mar 31, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.