Michael Farmwald
66Patents
46h-index
13Co-inventors
81Inventor score
Filing activity: Dec 1, 1989 → Sep 14, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5243703A | Apparatus for synchronously generating clock signals in a data processing system | Physics | 434 | Expired |
| US5319755A | Integrated circuit I/O using high performance bus interface | Emerging Cross-Sectional Technologies | 327 | Expired |
| US5606717A | Memory circuitry having bus interface for receiving information in packets and access time registers | Emerging Cross-Sectional Technologies | 284 | Expired |
| US5928343A | Memory module having memory devices containing internal device ID registers and method of initializing same | Emerging Cross-Sectional Technologies | 260 | Expired |
| US5513327A | Integrated circuit I/O using a high performance bus interface | Emerging Cross-Sectional Technologies | 218 | Expired |
| US5638334A | Integrated circuit I/O using a high performance bus interface | Emerging Cross-Sectional Technologies | 168 | Expired |
| US6101152A | Method of operating a synchronous memory device | Emerging Cross-Sectional Technologies | 160 | Expired |
| US5954804A | Synchronous memory device having an internal register | Emerging Cross-Sectional Technologies | 149 | Expired |
| US5430676A | Dynamic random access memory system | Physics | 146 | Expired |
| US6185644A | Memory system including a plurality of memory devices and a transceiver device | Emerging Cross-Sectional Technologies | 142 | Expired |
| US5915105A | Integrated circuit I/O using a high performance bus interface | Emerging Cross-Sectional Technologies | 137 | Expired |
| US6314051A | Memory device having write latency | Emerging Cross-Sectional Technologies | 137 | Expired |
| US5657481A | Memory device with a phase locked loop circuitry | Emerging Cross-Sectional Technologies | 135 | Expired |
| US5446696A | Method and apparatus for implementing refresh in a synchronous DRAM system | Physics | 131 | Expired |
| US6266285A | Method of operating a memory device having write latency | Emerging Cross-Sectional Technologies | 129 | Expired |
| US5953263A | Synchronous memory device having a programmable register and method of controlling same | Emerging Cross-Sectional Technologies | 127 | Expired |
| US6260097A | Method and apparatus for controlling a synchronous memory device | Emerging Cross-Sectional Technologies | 124 | Expired |
| US6584037B2 | Memory device which samples data after an amount of time transpires | Emerging Cross-Sectional Technologies | 119 | Expired |
| US6038195A | Synchronous memory device having a delay time register and method of operating same | Emerging Cross-Sectional Technologies | 114 | Expired |
| US5473575A | Integrated circuit I/O using a high performance bus interface | Emerging Cross-Sectional Technologies | 113 | Expired |
| US5995443A | Synchronous memory device | Emerging Cross-Sectional Technologies | 112 | Expired |
| US6032214A | Method of operating a synchronous memory device having a variable data output length | Emerging Cross-Sectional Technologies | 109 | Expired |
| US6034918A | Method of operating a memory having a variable data output length and a programmable register | Emerging Cross-Sectional Technologies | 107 | Expired |
| US6035365A | Dual clocked synchronous memory device having a delay time register and method of operating same | Emerging Cross-Sectional Technologies | 104 | Expired |
| US5841580A | Integrated circuit I/O using a high performance bus interface | Emerging Cross-Sectional Technologies | 102 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.