Apparatus for cooling semiconductor chips in multichip modules
US5514906A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1993 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Nov 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included. With the increased cooling efficiency, the height of each cooling channel may be substantially reduced to allow close stacking of interconnect substrates for three-dimensional packages and to shorten the vertical communication time between the interconnect substrat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.