Semiconductor memory device
US5515312A · kind A · utility
29Cited by
3References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Oct 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.