Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache
US5515522A · kind A · utility
16Cited by
9References
21Claims
0Family size
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Key dates
| Filing date | Feb 24, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.