High voltage lateral DMOS device with enhanced drift region
US5517046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1995 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Feb 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.