Random access memory and an improved bus arrangement therefor
US5517442A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1995 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Mar 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.