Structure and method for improved memory arrays and improved electrical contacts in semiconductor devices

US5519239A · kind A · utility

Assignee

• Catalyst Semiconductor, Inc. · US

Inventor

• Sam Chu · Baoshan, TW

Key dates

• Filing date: Nov 10, 1994
• Grant date: May 21, 1996
• Expiry date: Nov 10, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/905

Abstract

A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer to a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, th…