Datapath synthesis method and apparatus utilizing a structured cell library
US5519627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1994 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Nov 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic and control logic. The control logic is implemented in standard cells or gate arrays using a logic synthesizer. The datapath logic is optimally synthesized using a datapath synthesizer having a library of datapath elements, including both structural components and computational components, where some of the computational components are complex circuits having multiple, parallel outputs. Each computational component has associated therewith a set of one or more datapath expressions performed thereby. The received HDL circuit specification is converted into circuit data structures representing the circuit's datapath expressions and structural components. The datapath synthesizer locates all datapath elements in said library matching each such datapath expression and structural component. Then an optimizer determines which datapath expressions can be "combined", or performed by a single library element, so as to reduce the circuit layout area used. The optimizer can combine multiple datapath …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.