Semiconductor memory device having cell isolation structure
US5521407A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Nov 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.