Dielectric structure for anti-fuse programming element
US5521423A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Apr 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An antifuse element suitable for use in FPGA. When a device is miniaturized to reduce the write voltage in an antifuse element and as the film thickness of the antifuse dielectric film is being reduced, the dielectric breakdown voltage is greatly variable due to the irregularity of the underlying metal. If the dielectric film is formed by a metal oxide having a relatively high specific permitivity without changing its parasitic capacity as compared to the prior art, the film thickness of the dielectric film can be increased in comparison with oxide and nitride films formed according to the prior art. The irregularity of the underlying metal can be reduced by coating it with a metal nitride or TiB film or TiC film. To equalize the dielectric breakdown voltage, another insulation film having a film thickness such that the direct tunnel conduction is dominant is formed below the metal oxide. To reduce the irregularity of the metal surface and to reduce the resistance after dielectric breakdown, an amorphous silicon layer is deposited before the metal oxide is deposited thereover to form a laminated film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.