Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
US5521837A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1995 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Jan 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.