Clock synchronous semiconductor memory device
US5521878A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Sep 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.