Transistor fabrication method using dielectric protection layers to eliminate emitter defects

US5523244A · kind A · utility

Assignee

• Hughes Aircraft Company · US

Inventors

• Truc Q. Vu · Tustin, US
• Maw-Rong Chin · Tecate Mission Road, US
• Mei Li · Nanhu, CN

Key dates

• Filing date: Dec 19, 1994
• Grant date: Jun 4, 1996
• Expiry date: Dec 19, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/124

Abstract

A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform devic…