Method for avoiding lithographic rounding effects for semiconductor fabrication
US5523258A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1994 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Apr 29, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/948
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The use of separate masks to pattern the same layer of material formed over a semiconductor substrate serves to reduce or avoid lithographic rounding effects. A layer of material formed over a semiconductor substrate may be patterned in accordance with separate masks. A first mask may have a feature which is substantially perpendicular to a feature of a separate second mask. Where the layer is patterned to form transistor gates, the minimum amount each transistor gate should extend over the edge of its active region under the endcap rule may be reduced. In this regard, a line pattern mask and a gap mask are used to avoid lithographic rounding effects in forming the transistor gates. Semiconductor devices may thus be fabricated with higher packing densities as transistors may be placed closer to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.