Mark A. Helm
125Patents
12h-index
70Co-inventors
89Inventor score
Filing activity: Apr 29, 1994 → Mar 20, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5624863A | Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate | Emerging Cross-Sectional Technologies | 132 | Expired |
| US7755146B2 | Formation of standard voltage threshold and low voltage threshold MOSFET devices | Electricity | 122 | Active |
| US5534449A | Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry | Electricity | 73 | Expired |
| US5747855A | CMOS integrated circuitry with Halo and LDD regions | Electricity | 26 | Expired |
| US5523258A | Method for avoiding lithographic rounding effects for semiconductor fabrication | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7112488B2 | Source lines for NAND memory devices | Physics | 22 | Expired |
| US5776806A | Method of forming CMOS integrated circuitry having halo regions | Electricity | 21 | Expired |
| US6268250A | Efficient fabrication process for dual well type structures | Electricity | 19 | Expired |
| US6124616A | Integrated circuitry comprising halo regions and LDD regions | Electricity | 18 | Expired |
| US5683927A | Method of forming CMOS integrated circuitry | Electricity | 18 | Expired |
| US9070442B2 | Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods | Emerging Cross-Sectional Technologies | 17 | Active |
| US6004854A | Method of forming CMOS integrated circuitry | Electricity | 13 | Expired |
| US5970335A | Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate | Emerging Cross-Sectional Technologies | 12 | Expired |
| US9947418B2 | Boosted channel programming of memory | Physics | 11 | Active |
| US7499325B2 | Flash memory device with improved erase operation | Physics | 11 | Active |
| US8203876B2 | Reducing effects of erase disturb in a memory device | Physics | 9 | Active |
| US9607692B2 | Threshold voltage distribution determination | Physics | 8 | Active |
| US9754683B2 | Method and system to obtain state confidence data using multistrobe read of a non-volatile memory | Physics | 8 | Active |
| US6261888A | Method of forming CMOS integrated circuitry | Electricity | 7 | Expired |
| US6635530B2 | Methods of forming gated semiconductor assemblies | Electricity | 7 | Expired |
| US9159736B2 | Data line arrangement and pillar arrangement in apparatuses | Electricity | 6 | Active |
| US6358787B2 | Method of forming CMOS integrated circuitry | Electricity | 6 | Expired |
| US6756634B2 | Gated semiconductor assemblies | Electricity | 6 | Expired |
| US6849492B2 | Method for forming standard voltage threshold and low voltage threshold MOSFET devices | Electricity | 6 | Expired |
| US7701780B2 | Non-volatile memory cell healing | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.