Integrated circuit device structure with dielectric and metal stacked plug in contact hole
US5523624A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1993 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Aug 26, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.