Low noise low voltage phase lock loop
US5523723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1995 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | May 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0322
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.