Converting biased exponents from single/double precision to extended precision without requiring an adder
US5523961A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1994 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Oct 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.