Method and apparatus for verifying the programming of multi-level flash EEPROM memory
US5523972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1994 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Jun 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming verify circuit for controlling the memory cells to which programming voltages are applied, the circuit including a comparator for testing the state of each cell being programmed with the state to which the cell is being programmed, and a program load circuit which responds to the result of the test by the comparator to hold a condition for each memory cell being programmed to indicate whether the memory cell should be further programmed, each program load circuit including circuitry for precluding the holding of a condition indicating further programming is necessary once the associated memory cell has been initially verified as programmed by the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.