Bipolar transistor
US5525817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1993 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Sep 20, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/011
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.