Serial access memory device
US5526316A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1994 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Apr 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The serial access memory device provided has a first data terminal and a memory cell array having a plurality of address locations. The serial access memory device comprises a shift register and an address decode circuit. The shift register, responsive to an address clock signal, stores a first address value of a serial access memory operation. The shift register has an input terminal coupled to the first data terminal. The address decode circuit serially accesses the plurality of address locations of the memory cell array, responsive to an access control signal, the first address value, the address clock signal and the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.