Apparatus for entering and executing test mode operations for memory
US5526364A · kind A · utility
83Cited by
1References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating test-mode signals for memory which uses both hardware and software protection schemes. The circuit enters a test code by receiving a high voltage at two terminals. The high voltage must remain on at least one of the terminals during the test code process. Otherwise, the circuit is reset. The test code contains test code bits and format code bits. The format code bits are the same for all test codes and distinguish the test codes from commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.