System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions
US5526500A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.