Method to prevent latch-up and improve breakdown volatge in SOI mosfets
US5527724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1994 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Sep 12, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/04
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improved radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant an electrically neutral in silicon impurity atom such as krypton, xenon or germanium into the device to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.