Logic signal validity verification apparatus
US5528165A · kind A · utility
4Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1995 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Jun 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.