Sense amplifier having selectable power and speed modes
US5530384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase. Thus, the present invention accelerates the low-to-high signal transition on the amplified bitline in the low power mode. If the signal on the wordline is either a constant high or low, then the additional pull-up is disabled, thereby conserving power during the low power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.