Frequency multiplier circuit
US5530387A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 1995 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Jan 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier circuit comprising a first delay circuit for delaying sequentially a reference clock signal, a frequency doubler for delaying the reference clock signal and combining logically the delayed reference clock signal and the reference clock signal, a second delay circuit for delaying sequentially an output signal from the frequency doubler, a signal detector for logically combining the output signal from the frequency doubler and a plurality of output signals from the second delay circuit to detect a desired duty factor of signal, a decoder for decoding a plurality of output signals from the first delay circuit and a plurality of output signals from the signal detector to output a signal delayed by n times half a period of the reference clock signal, and a frequency generator for logically combining an output signal from the decoder and the reference clock signal to generate a multiple frequency of that of the reference clock signal. According to the present invention, the frequency multiplier circuit can automatically adjust an operating point regardless of a variation in a temperature or a process parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.