Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
US5530933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.