Patterned susceptor to reduce electrostatic force in a CVD chamber
US5531835A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1994 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | May 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A susceptor or other semiconductor wafer processing and/or transfer support platform includes a surface pattern having two or more regions of high and low elevation. The regions of high and low elevations can be rectangular/square dimpled patterns having tops coplanar with one another to support a semiconductor wafer for processing. The high and low regions can also be a wave form appearing to emanate from a point, where each of the wave crests form an imaginary plane on which a wafer to be processed can rest. The combination of high and low regions increases the average spacing between the wafer and the susceptor and reduces or eliminates the capacitive coupling (or sticking force) between processing hardware and a substrate (wafer) created by electrical fields during processing. The dimpled patterns are created by machining and can be created by using chemical and electrochemical etching of the wafer handling surfaces of processing hardware pieces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.