Techniques for via formation and filling
US5532516A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1995 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Mar 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.