Self refresh control circuit for memory cell array
US5532968A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1995 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Feb 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self refresh control circuit for a memory cell array including a plurality of address buffers for inputting addresses of the memory cell array and a plurality of decoders for decoding the addresses from the address buffers. The self refresh control circuit further includes a self refresh mode control circuit for controlling a self refresh operation of the memory cell array in response to a row address strobe signal and a column address strobe signal, a reference voltage generator for generating a plurality of reference voltages, each of the reference voltages being nearly constant in level regardless of a temperature variation in a chip, and a temperature tracing circuit for generating a voltage variable with the temperature variation in the chip, comparing the generated variable voltage with the reference voltages from the reference voltage generator, respectively, selecting a desired one of a plurality of self refresh periods from the self refresh mode control circuit in accordance with the compared results and outputting the selected self refresh period to the self refresh mode control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.