No latency pipeline
US5532970A · kind A · utility
6Cited by
3References
8Claims
0Family size
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.