Nonvolatile semiconductor memory having enhanced speed for erasing and programming
US5532971A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1994 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Dec 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.