Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests
US5534786A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1995 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Feb 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is an improved burn-in and test method of semiconductor wafers each having numerous integrated circuits formed therein. It includes the steps of dividing each semiconductor wafer into blocks each including some integrated circuits; giving each block an address to indicate in which part of the semiconductor wafer the integrated circuits of the block are placed; recording the addresses of all blocks; preparing burn-in boards each having sockets to detachably hold carriers each bearing an identification code; loading each carrier with a block to be tested; fitting each carrier in a selected socket in the burn-in board; and carrying out the burn-in and required tests on the blocks of each burn-in board. Analysis of test results permits the locating of defective integrated circuits, if any in semiconductor wafers in terms of the recorded addresses of the blocks and the identification codes of the carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.