On-chip ECC status
US5535226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1994 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | May 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, a memory device employing device-level error correction tracks the status of the error correction in terms of whether error correction is active or inactive, whether an uncorrectable error beyond the capability of the device-level correction is detected, whether a recovery option from an uncorrectable error is active and whether the recovery option has been reset. In another aspect, a diagnostic method for determining a status for one or more aspects of device-level error correction employed by a memory device is provided. In the diagnostic method, the status is determined for the one or more aspects, a flag is set based on the status, the flag is latched, a diagnostic code is input into the memory device and the latched flag is read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.