Method for mapping in logic synthesis by logic classification
US5537330A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Jun 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method within a logic synthesis system provides for using tags attached to the nodes in a parse string generated from an abstract description of a logic design to classify portions of a heterogeneous design as open control, structure dominant, or direct map. The classification is then used to govern the amount of optimization allowed during logic synthesis. The classification is further used to seed or bypass the covering algorithms to produce the technology implementation desired by the designer. Structure dominance is a technique for "seeding" patterns by a designer which best fit the structure to the technology, which implies that the structural representation of the design as entered by the designer dominates the patterns located by the covering algorithm. However, other pattern matching functions are allowed to find better matches, if they exist, and the covering algorithm is allowed the final choice. Direct map processing bypasses optimization and covering altogether to implement the structural representation exactly as written, if possible, using the available elements in the target technology library. In the event that direct map is not possible, the node is processed as …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.