Robert L. Kanzelman
75Patents
8h-index
26Co-inventors
78Inventor score
Filing activity: Jun 10, 1994 → Dec 10, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5537330A | Method for mapping in logic synthesis by logic classification | Physics | 45 | Expired |
| US6763505B2 | Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs | Physics | 18 | Expired |
| US5799170A | Simplified buffer manipulation using standard repowering function | Physics | 17 | Expired |
| US7260799B2 | Exploiting suspected redundancy for enhanced design verification | Physics | 15 | Expired |
| US6748573B2 | Apparatus and method for removing effects of phase abstraction from a phase abstracted trace | Physics | 11 | Expired |
| US7448005B2 | Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver | Physics | 10 | Active |
| US7266795B2 | System and method for engine-controlled case splitting within multiple-engine based verification framework | Physics | 9 | Expired |
| US6745377B2 | Apparatus and method for representing gated-clock latches for phase abstraction | Physics | 9 | Expired |
| US7315996B2 | Method and system for performing heuristic constraint simplification | Physics | 8 | Expired |
| US7210109B2 | Equivalence checking of scan path flush operations | Physics | 8 | Expired |
| US8146034B2 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. | Physics | 7 | Active |
| US7380222B2 | Method and system for performing minimization of input count during structural netlist overapproximation | Physics | 7 | Expired |
| US7934180B2 | Incremental speculative merging | Physics | 7 | Active |
| US7356792B2 | Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Physics | 7 | Expired |
| US7779378B2 | Computer program product for extending incremental verification of circuit design to encompass verification restraints | Physics | 7 | Active |
| US8578311B1 | Method and system for optimal diameter bounding of designs with complex feed-forward components | Physics | 6 | Active |
| US7350169B2 | Method and system for enhanced verification through structural target decomposition | Physics | 6 | Expired |
| US7509605B2 | Extending incremental verification of circuit design to encompass verification restraints | Physics | 6 | Active |
| US8181131B2 | Enhanced analysis of array-based netlists via reparameterization | Physics | 5 | Active |
| US7093218B2 | Incremental, assertion-based design verification | Physics | 5 | Expired |
| US7788616B2 | Method and system for performing heuristic constraint simplification | Physics | 5 | Active |
| US7340694B2 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Physics | 5 | Expired |
| US7793242B2 | Method and system for performing heuristic constraint simplification | Physics | 5 | Active |
| US7360185B2 | Design verification using sequential and combinational transformations | Physics | 5 | Expired |
| US7370292B2 | Method for incremental design reduction via iterative overapproximation and re-encoding strategies | Physics | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.