Memory in integrated circuit form with improved reading time
US5537349A · kind A · utility
9Cited by
10References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random-access memory with an accelerated access time. One or more of the preliminary operations of the sequence of operations carried out for accessing the memory are anticipated by performing the anticipated operation or operations during the end of a sequence of a previous memory access. The anticipated operation is preferably that of the deselection of the bit lines of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.