High resolution phase edge lithography without the need for a trim mask
US5538833A · kind A · utility
24Cited by
3References
3Claims
0Family size
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Key dates
| Filing date | Aug 3, 1994 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Aug 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/34
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A process of phase edge lithography is employed in the manufacture of very large scale integrated (VLSI) chips in which chrome images are biased on a phase edge of a phase shift mask (PSM) and the mask overexposed to compensate for the positive bias. This overexposure eliminates any residual images from the phase edge mask with minimum impact to the desired images. This simple process results in a trim-less phase edge process that takes advantage of the improved resolution and process latitude of phase edge PSMs while avoiding layout impacts caused by a trim mask or other phase edge elimination methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.