Write verify schemes for flash memory with multilevel cells
US5539690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1994 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jun 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.t voltage level of the selected flash cell, rather than to determine the data of the selected flash cell, as is done for the first embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.